As semiconductor devices scale to smaller dimensions, the ability to harness device improvements with decreased size becomes more challenging. The synthesis of three-dimensional semiconductor transistors, such as fin type field effect transistors (finFET), involves challenging processing issues. In many finFET designs, an array of fins may be formed, wherein at least a portion of this array of fins is to be removed during device fabrication. So-called fin cutting processes may employ masks to protect fins not to be removed, while creating fin cut regions to expose other fins to be removed. Because of overlay and etching issues, the fins targeted for removal may be incompletely etched using known anisotropic etching processes, leaving fin remnants such as so-called fin spikes, where the fin spikes may protrude above the surface of isolation oxide. Notably, the fin spikes, being formed of semiconductor material such as silicon, may be removed using isotropic etching. This approach carries the unwanted side-effect of etching silicon fins in a lateral direction, so the length of the fins may be unduly reduced.
With respect to these and other considerations, the present disclosure is provided.